1. Field of the Invention
The present invention relates to digital signal processing, including computer arithmetic, low-power and high-speed architectures and, more particularly, to blocks for low-area multipliers, and in general for complex signal processing involving multiplications with variable coefficients, such as scalable FFT, adaptive digital filters, and any kind of application that requires multiplying a N-bit signal with a M-bit dynamic coefficient, and related methodology.
2. Description of the Related Art
Canonic Signed Digit (CSD) encoding/decoding operations are well known, and a significant literature exists on that topic. In A. Peled, “On the hardware implementation of digital signal processors”, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 24(1), pp. 76-78, February 1976, the Canonic Signed Digit encoding properties have been extensively explored.
Binary Canonic Signed Digit (BCSD) encoding has been introduced in R. Hashemian, “A New Method for Conversion of a Two Complement to Canonic Signed Digit Number System and its Representation”, IEEE Thirtieth Asilomar Conference on Signals Systems and Computers, vol. 2, pp. 904-906, November 1996, with special emphasis placed on computer programming. This document discloses an algorithm that performs the Binary Canonic Signed Digit encoding of a number in two's complement notation using a procedure written in C language. The procedure proposed is not suitable for hardware implementation.
Moreover, no mention is made of any Binary Canonic Signed Digit decoding process, “decoding” being intended to designate the process aimed at recovering the Canonic Signed Digit notation for subsequent Canonic Signed Digit processing.
A further document of interest in this area is U.S. Pat. No. 4,623,872, which discloses a circuit for CSD-coding of binary numbers represented in two's complement.